referred to as machine instructions or computer instructions. The collection of different instructions that the processor can execute is referred to as the processor’s
instruction set.
Elements of a Machine Instruction
Each instruction must contain the information required by the processor for execution. Figure 12.1, which repeats Figure 3.6, shows the steps involved in instruction
execution and, by implication, defines the elements of a machine instruction. These
elements are as follows:
• Operation code: Specifies the operation to be performed (e.g., ADD, I/O).
The operation is specified by a binary code, known as the operation code, or
opcode.
• Source operand reference: The operation may involve one or more source
operands, that is, operands that are inputs for the operation.
Figure 12.1 Instruction Cycle State Diagram
• Next instruction reference: This tells the processor where to fetch the next
instruction after the execution of this instruction is complete.
The address of the next instruction to be fetched could be either a real address
or a virtual address, depending on the architecture. Generally, the distinction is
transparent to the instruction set architecture. In most cases, the next instruction to
be fetched immediately follows the current instruction. In those cases, there is no
explicit reference to the next instruction. When an explicit reference is needed, then
the main memory or virtual memory address must be supplied. The form in which
that address is supplied is discussed in Chapter 13.
Source and result operands can be in one of four areas:
• Main or virtual memory: As with next instruction references, the main or virtual memory address must be supplied.
• Processor register: With rare exceptions, a processor contains one or more
registers that may be referenced by machine instructions. If only one register
exists, reference to it may be implicit. If more than one register exists, then
each register is assigned a unique name or number, and the instruction must
contain the number of the desired register.
• Immediate: The value of the operand is contained in a field in the instruction
being executed.
• I/O device: The instruction must specify the I/O module and device for the
operation. If memory-mapped I/O is used, this is just another main or virtual
memory address.
Instruction Representation
Within the computer, each instruction is represented by a sequence of bits. The
instruction is divided into fields, corresponding to the constituent elements of the
Figure 12.2 A Simple Instruction Format
instruction. A simple example of an instruction format is shown in Figure 12.2. As
another example, the IAS instruction format is shown in Figure 2.2. With most
instruction sets, more than one format is used. During instruction execution, an
instruction is read into an instruction register (IR) in the processor. The processor
must be able to extract the data from the various instruction fields to perform the
required operation.
It is difficult for both the programmer and the reader of textbooks to deal with
binary representations of machine instructions. Thus, it has become common practice to use a symbolic representation of machine instructions. An example of this
was used for the IAS instruction set, in Table 2.1.
Opcodes are represented by abbreviations, called mnemonics, that indicate
the operation. Common examples include
another example, the IAS instruction format is shown in Figure 2.2. With most
instruction sets, more than one format is used. During instruction execution, an
instruction is read into an instruction register (IR) in the processor. The processor
must be able to extract the data from the various instruction fields to perform the
required operation.
It is difficult for both the programmer and the reader of textbooks to deal with
binary representations of machine instructions. Thus, it has become common practice to use a symbolic representation of machine instructions. An example of this
was used for the IAS instruction set, in Table 2.1.
Opcodes are represented by abbreviations, called mnemonics, that indicate
the operation. Common examples include
ADD Add
SUB Subtract
MUL Multiply
DIV Divide
LOAD Load data from memory
STOR Store data to memory
Operands are also represented symbolically. For example, the instruction
ADD R, Y
may mean add the value contained in data location Y to the contents of register R.In this example, Y refers to the address of a location in memory, and R refers to a
particular register. Note that the operation is performed on the contents of a location, not on its address.
Thus, it is possible to write a machine-language program in symbolic form.
Each symbolic opcode has a fixed binary representation, and the programmer specifies the location of each symbolic operand. For example, the programmer might
begin with a list of definitions:
X = 513
Y = 514
and so on. A simple program would accept this symbolic input, convert opcodes andoperand references to binary form, and construct binary machine instructions.
Machine-language programmers are rare to the point of nonexistence. Most programs today are written in a high-level language or, failing that, assembly language,
which is discussed in Appendix B. However, symbolic machine language remains a
useful tool for describing machine instructions, and we will use it for that purpose.
Instruction Types
Consider a high-level language instruction that could be expressed in a language
such as BASIC or FORTRAN. For example,
such as BASIC or FORTRAN. For example,
X = X + Y
This statement instructs the computer to add the value stored in Y to the valuestored in X and put the result in X. How might this be accomplished with machine
instructions? Let us assume that the variables X and Y correspond to locations 513
and 514. If we assume a simple set of machine instructions, this operation could be
accomplished with three instructions:
1. Load a register with the contents of memory location 513.
2. Add the contents of memory location 514 to the register.
3. Store the contents of the register in memory location 513.
As can be seen, the single BASIC instruction may require three machine
instructions. This is typical of the relationship between a high-level language and
a machine language. A high-level language expresses operations in a concise algebraic form, using variables. A machine language expresses operations in a basic
form involving the movement of data to or from registers.
With this simple example to guide us, let us consider the types of instructions
that must be included in a practical computer. A computer should have a set of
instructions that allows the user to formulate any data processing task. Another way
to view it is to consider the capabilities of a high-level programming language. Any
program written in a high-level language must be translated into machine language
to be executed. Thus, the set of machine instructions must be sufficient to express
any of the instructions from a high-level language. With this in mind we can categorize instruction types as follows:
• Data processing: Arithmetic and logic instructions
• Data storage: Movement of data into or out of register and or memory
locations
• Data movement: I/O instructions
• Control: Test and branch instructions
Arithmetic instructions provide computational capabilities for processing
numeric data. Logic (Boolean) instructions operate on the bits of a word as bits
rather than as numbers; thus, they provide capabilities for processing any other type
of data the user may wish to employ. These operations are performed primarily on
data in processor registers. Therefore, there must be memory instructions for moving data between memory and the registers. I/O instructions are needed to transfer
programs and data into memory and the results of computations back out to the
user. Test instructions are used to test the value of a data word or the status of
a computation. Branch instructions are then used to branch to a different set of
instructions depending on the decision made.
We will examine the various types of instructions in greater detail later in this
chapter.'
3. Store the contents of the register in memory location 513.
As can be seen, the single BASIC instruction may require three machine
instructions. This is typical of the relationship between a high-level language and
a machine language. A high-level language expresses operations in a concise algebraic form, using variables. A machine language expresses operations in a basic
form involving the movement of data to or from registers.
With this simple example to guide us, let us consider the types of instructions
that must be included in a practical computer. A computer should have a set of
instructions that allows the user to formulate any data processing task. Another way
to view it is to consider the capabilities of a high-level programming language. Any
program written in a high-level language must be translated into machine language
to be executed. Thus, the set of machine instructions must be sufficient to express
any of the instructions from a high-level language. With this in mind we can categorize instruction types as follows:
• Data processing: Arithmetic and logic instructions
• Data storage: Movement of data into or out of register and or memory
locations
• Data movement: I/O instructions
• Control: Test and branch instructions
Arithmetic instructions provide computational capabilities for processing
numeric data. Logic (Boolean) instructions operate on the bits of a word as bits
rather than as numbers; thus, they provide capabilities for processing any other type
of data the user may wish to employ. These operations are performed primarily on
data in processor registers. Therefore, there must be memory instructions for moving data between memory and the registers. I/O instructions are needed to transfer
programs and data into memory and the results of computations back out to the
user. Test instructions are used to test the value of a data word or the status of
a computation. Branch instructions are then used to branch to a different set of
instructions depending on the decision made.
We will examine the various types of instructions in greater detail later in this
chapter.'
Number of Addresses
One of the traditional ways of describing processor architecture is in terms of the
number of addresses contained in each instruction. This dimension has become less
significant with the increasing complexity of processor design. Nevertheless, it is
useful at this point to draw and analyze this distinction.
What is the maximum number of addresses one might need in an instruction? Evidently, arithmetic and logic instructions will require the most operands.
Virtually all arithmetic and logic operations are either unary (one source operand)
or binary (two source operands). Thus, we would need a maximum of two addresses
to reference source operands. The result of an operation must be stored, suggesting
a third address, which defines a destination operand. Finally, after completion of an
instruction, the next instruction must be fetched, and its address is needed.
This line of reasoning suggests that an instruction could plausibly be required
to contain four address references: two source operands, one destination operand,
and the address of the next instruction. In most architectures, most instructions have
one, two, or three operand addresses, with the address of the next instruction being
implicit (obtained from the program counter). Most architectures also have a few
special-purpose instructions with more operands. For example, the load and store
multiple instructions of the ARM architecture, described in Chapter 13, designate
up to 17 register operands in a single instruction.
Figure 12.3 compares typical one-, two-, and three-address instructions that
could be used to compute Y = (A - B)>[C + (D * E)]. With three addresses,
each instruction specifies two source operand locations and a destination operand
location. Because we choose not to alter the value of any of the operand locations,
a temporary location, T, is used to store some intermediate results. Note that there
are four instructions and that the original expression had five operands
number of addresses contained in each instruction. This dimension has become less
significant with the increasing complexity of processor design. Nevertheless, it is
useful at this point to draw and analyze this distinction.
What is the maximum number of addresses one might need in an instruction? Evidently, arithmetic and logic instructions will require the most operands.
Virtually all arithmetic and logic operations are either unary (one source operand)
or binary (two source operands). Thus, we would need a maximum of two addresses
to reference source operands. The result of an operation must be stored, suggesting
a third address, which defines a destination operand. Finally, after completion of an
instruction, the next instruction must be fetched, and its address is needed.
This line of reasoning suggests that an instruction could plausibly be required
to contain four address references: two source operands, one destination operand,
and the address of the next instruction. In most architectures, most instructions have
one, two, or three operand addresses, with the address of the next instruction being
implicit (obtained from the program counter). Most architectures also have a few
special-purpose instructions with more operands. For example, the load and store
multiple instructions of the ARM architecture, described in Chapter 13, designate
up to 17 register operands in a single instruction.
Figure 12.3 compares typical one-, two-, and three-address instructions that
could be used to compute Y = (A - B)>[C + (D * E)]. With three addresses,
each instruction specifies two source operand locations and a destination operand
location. Because we choose not to alter the value of any of the operand locations,
a temporary location, T, is used to store some intermediate results. Note that there
are four instructions and that the original expression had five operands
Three-address instruction formats are not common because they require a
relatively long instruction format to hold the three address references. With twoaddress instructions, and for binary operations, one address must do double duty as
both an operand and a result. Thus, the instruction SUB Y, B carries out the calculation Y - B and stores the result in Y. The two-address format reduces the space
requirement but also introduces some awkwardness. To avoid altering the value of
an operand, a MOVE instruction is used to move one of the values to a result or
temporary location before performing the operation. Our sample program expands
to six instructions.
Simpler yet is the one-address instruction. For this to work, a second address
must be implicit. This was common in earlier machines, with the implied address
being a processor register known as the accumulator (AC). The accumulator contains one of the operands and is used to store the result. In our example, eight
instructions are needed to accomplish the task.
It is, in fact, possible to make do with zero addresses for some instructions.
Zero-address instructions are applicable to a special memory organization called
a stack. A stack is a last-in-first-out set of locations. The stack is in a known location and, often, at least the top two elements are in processor registers. Thus,
zero-address instructions would reference the top two stack elements. Stacks are
described in Appendix O. Their use is explored further later in this chapter and in
Chapter 13.
Table 12.1 summarizes the interpretations to be placed on instructions with
zero, one, two, or three addresses. In each case in the table, it is assumed that the
address of the next instruction is implicit, and that one operation with two source
operands and one result operand is to be performed.
The number of addresses per instruction is a basic design decision. Fewer
addresses per instruction result in instructions that are more primitive, requiring a
less complex processor. It also results in instructions of shorter length. On the other
hand, programs contain more total instructions, which in general results in longer
execution times and longer, more complex programs. Also, there is an important
threshold between one-address and multiple-address instructions. With one-address
instructions, the programmer generally has available only one general-purpose register, the accumulator. With multiple-address instructions, it is common to have
multiple general-purpose registers. This allows some operations to be performer.
relatively long instruction format to hold the three address references. With twoaddress instructions, and for binary operations, one address must do double duty as
both an operand and a result. Thus, the instruction SUB Y, B carries out the calculation Y - B and stores the result in Y. The two-address format reduces the space
requirement but also introduces some awkwardness. To avoid altering the value of
an operand, a MOVE instruction is used to move one of the values to a result or
temporary location before performing the operation. Our sample program expands
to six instructions.
Simpler yet is the one-address instruction. For this to work, a second address
must be implicit. This was common in earlier machines, with the implied address
being a processor register known as the accumulator (AC). The accumulator contains one of the operands and is used to store the result. In our example, eight
instructions are needed to accomplish the task.
It is, in fact, possible to make do with zero addresses for some instructions.
Zero-address instructions are applicable to a special memory organization called
a stack. A stack is a last-in-first-out set of locations. The stack is in a known location and, often, at least the top two elements are in processor registers. Thus,
zero-address instructions would reference the top two stack elements. Stacks are
described in Appendix O. Their use is explored further later in this chapter and in
Chapter 13.
Table 12.1 summarizes the interpretations to be placed on instructions with
zero, one, two, or three addresses. In each case in the table, it is assumed that the
address of the next instruction is implicit, and that one operation with two source
operands and one result operand is to be performed.
The number of addresses per instruction is a basic design decision. Fewer
addresses per instruction result in instructions that are more primitive, requiring a
less complex processor. It also results in instructions of shorter length. On the other
hand, programs contain more total instructions, which in general results in longer
execution times and longer, more complex programs. Also, there is an important
threshold between one-address and multiple-address instructions. With one-address
instructions, the programmer generally has available only one general-purpose register, the accumulator. With multiple-address instructions, it is common to have
multiple general-purpose registers. This allows some operations to be performer.
solely on registers. Because register references are faster than memory references,
this speeds up execution. For reasons of flexibility and ability to use multiple registers, most contemporary machines employ a mixture of two- and three-address
instructions.
The design trade-offs involved in choosing the number of addresses per instruction are complicated by other factors. There is the issue of whether an address references a memory location or a register. Because there are fewer registers, fewer bits
are needed for a register reference. Also, as we shall see in Chapter 13, a machine
may offer a variety of addressing modes, and the specification of mode takes one or
more bits. The result is that most processor designs involve a variety of instruction
formats.
this speeds up execution. For reasons of flexibility and ability to use multiple registers, most contemporary machines employ a mixture of two- and three-address
instructions.
The design trade-offs involved in choosing the number of addresses per instruction are complicated by other factors. There is the issue of whether an address references a memory location or a register. Because there are fewer registers, fewer bits
are needed for a register reference. Also, as we shall see in Chapter 13, a machine
may offer a variety of addressing modes, and the specification of mode takes one or
more bits. The result is that most processor designs involve a variety of instruction
formats.
Instruction Set Design
One of the most interesting, and most analyzed, aspects of computer design is
instruction set design. The design of an instruction set is very complex because it
affects so many aspects of the computer system. The instruction set defines many
of the functions performed by the processor and thus has a significant effect on the
implementation of the processor. The instruction set is the programmer’s means of
controlling the processor. Thus, programmer requirements must be considered in
designing the instruction set.
It may surprise you to know that some of the most fundamental issues relating to the design of instruction sets remain in dispute. Indeed, in recent years, the
level of disagreement concerning these fundamentals has actually grown. The most
important of these fundamental design issues include the following:
• Operation repertoire: How many and which operations to provide, and how
complex operations should be
• Data types: The various types of data upon which operations are performed
• Instruction format: Instruction length (in bits), number of addresses, size of
various fields, and so on
• Registers: Number of processor registers that can be referenced by instructions, and their use
• Addressing: The mode or modes by which the address of an operand is
specified
These issues are highly interrelated and must be considered together in designing an instruction set. This book, of course, must consider them in some sequence,
but an attempt is made to show the interrelationships.
Because of the importance of this topic, much of Part Three is devoted to
instruction set design. Following this overview section, this chapter examines data
types and operation repertoire. Chapter 13 examines addressing modes (which
includes a consideration of registers) and instruction formats. Chapter 15 examines
the reduced instruction set computer (RISC). RISC architecture calls into question many of the instruction set design decisions traditionally made in commercial
computers.
instruction set design. The design of an instruction set is very complex because it
affects so many aspects of the computer system. The instruction set defines many
of the functions performed by the processor and thus has a significant effect on the
implementation of the processor. The instruction set is the programmer’s means of
controlling the processor. Thus, programmer requirements must be considered in
designing the instruction set.
It may surprise you to know that some of the most fundamental issues relating to the design of instruction sets remain in dispute. Indeed, in recent years, the
level of disagreement concerning these fundamentals has actually grown. The most
important of these fundamental design issues include the following:
• Operation repertoire: How many and which operations to provide, and how
complex operations should be
• Data types: The various types of data upon which operations are performed
• Instruction format: Instruction length (in bits), number of addresses, size of
various fields, and so on
• Registers: Number of processor registers that can be referenced by instructions, and their use
• Addressing: The mode or modes by which the address of an operand is
specified
These issues are highly interrelated and must be considered together in designing an instruction set. This book, of course, must consider them in some sequence,
but an attempt is made to show the interrelationships.
Because of the importance of this topic, much of Part Three is devoted to
instruction set design. Following this overview section, this chapter examines data
types and operation repertoire. Chapter 13 examines addressing modes (which
includes a consideration of registers) and instruction formats. Chapter 15 examines
the reduced instruction set computer (RISC). RISC architecture calls into question many of the instruction set design decisions traditionally made in commercial
computers.
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