The x86 can deal with data types of 8 (byte), 16 (word), 32 (doubleword), 64 (quadword), and 128 (double quadword) bits in length. To allow maximum flexibility in
data structures and efficient memory utilization, words need not be aligned at evennumbered addresses; doublewords need not be aligned at addresses evenly divisible
by 4; and quadwords need not be aligned at addresses evenly divisible by 8; and
so on. However, when data are accessed across a 32-bit bus, data transfers take
place in units of doublewords, beginning at addresses divisible by 4. The processor
converts the request for misaligned values into a sequence of requests for the bus
transfer. As with all of the Intel 80x86 machines, the x86 uses the little-endian style;
that is, the least significant byte is stored in the lowest address (see Appendix 12A
for a discussion of endianness).
The byte, word, doubleword, quadword, and double quadword are referred to
as general data types. In addition, the x86 supports an impressive array of specific
data types that are recognized and operated on by particular instructions. Table 12.2
summarizes these types.
Figure 12.4 illustrates the x86 numerical data types. The signed integers are in
twos complement representation and may be 16, 32, or 64 bits long. The floatingpoint type actually refers to a set of types that are used by the floating-point unit
and operated on by floating-point instructions. The three floating-point representations conform to the IEEE 754 standard.
The packed SIMD (single-instruction-multiple-data) data types were introduced to the x86 architecture as part of the extensions of the instruction set to
optimize performance of multimedia applications. These extensions include MMX
(multimedia extensions) and SSE (streaming SIMD extensions). The basic concept
is that multiple operands are packed into a single referenced memory item and that
these multiple operands are operated on in parallel. The data types are as follows:
• Packed byte and packed byte integer: Bytes packed into a 64-bit quadword or
128-bit double quadword, interpreted as a bit field or as an integer
• Packed word and packed word integer: 16-bit words packed into a 64-bit quadword or 128-bit double quadword, interpreted as a bit field or as an integer
• Packed doubleword and packed doubleword integer: 32-bit doublewords
packed into a 64-bit quadword or 128-bit double quadword, interpreted as a
bit field or as an integer
• Packed quadword and packed qaudword integer: Two 64-bit quadwords
packed into a 128-bit double quadword, interpreted as a bit field or as an integer
• Packed single-precision floating-point and packed double-precision floatingpoint: Four 32-bit floating-point or two 64-bit floating-point values packed
into a 128-bit double quadword
packed into a 64-bit quadword or 128-bit double quadword, interpreted as a
bit field or as an integer
• Packed quadword and packed qaudword integer: Two 64-bit quadwords
packed into a 128-bit double quadword, interpreted as a bit field or as an integer
• Packed single-precision floating-point and packed double-precision floatingpoint: Four 32-bit floating-point or two 64-bit floating-point values packed
into a 128-bit double quadword
ARM Data Types
ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits
in length. Normally, halfword access should be halfword aligned and word accesses
should be word aligned. For nonaligned access attempts, the architecture supports
three alternatives.
• Default case:
– The address is treated as truncated, with address bits[1:0] treated as zero
for word accesses, and address bit[0] treated as zero for halfword accesses.
in length. Normally, halfword access should be halfword aligned and word accesses
should be word aligned. For nonaligned access attempts, the architecture supports
three alternatives.
• Default case:
– The address is treated as truncated, with address bits[1:0] treated as zero
for word accesses, and address bit[0] treated as zero for halfword accesses.
the word-aligned data transferred by a non word-aligned address one, two, or
three bytes depending on the value of the two least significant address bits.
• Alignment checking: When the appropriate control bit is set, a data abort signal indicates an alignment fault for attempting unaligned access.
• Unaligned access: When this option is enabled, the processor uses one or more
memory accesses to generate the required transfer of adjacent bytes transparently to the programmer.
For all three data types (byte, halfword, and word) an unsigned interpretation
is supported, in which the value represents an unsigned, nonnegative integer. All
three data types can also be used for twos complement signed integers.
The majority of ARM processor implementations do not provide floatingpoint hardware, which saves power and area. If floating-point arithmetic is required
in such processors, it must be implemented in software. ARM does support an
optional floating-point coprocessor that supports the single- and double-precision
floating point data types defined in IEEE 754.
ENDIAN SUPPORT A state bit (E-bit) in the system control register is set and cleared
under program control using the SETEND instruction. The E-bit defines which
endian to load and store data. Figure 12.5 illustrates the functionality associated
with the E-bit for a word load or store operation. This mechanism enables efficient
dynamic data load/store for system designers who know they need to access data
structures in the opposite endianness to their OS/environment. Note that the address
of each data byte is fixed in memory. However, the byte lane in a register is different.
0 Komentar